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Viewing File: /usr/src/kernels/5.14.0-570.30.1.el9_6.x86_64/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779f0 CPG Core Clocks */
#define R8A779F0_CLK_ZX 0
#define R8A779F0_CLK_ZS 1
#define R8A779F0_CLK_ZT 2
#define R8A779F0_CLK_ZTR 3
#define R8A779F0_CLK_S0D2 4
#define R8A779F0_CLK_S0D3 5
#define R8A779F0_CLK_S0D4 6
#define R8A779F0_CLK_S0D2_MM 7
#define R8A779F0_CLK_S0D3_MM 8
#define R8A779F0_CLK_S0D4_MM 9
#define R8A779F0_CLK_S0D2_RT 10
#define R8A779F0_CLK_S0D3_RT 11
#define R8A779F0_CLK_S0D4_RT 12
#define R8A779F0_CLK_S0D6_RT 13
#define R8A779F0_CLK_S0D3_PER 14
#define R8A779F0_CLK_S0D6_PER 15
#define R8A779F0_CLK_S0D12_PER 16
#define R8A779F0_CLK_S0D24_PER 17
#define R8A779F0_CLK_S0D2_HSC 18
#define R8A779F0_CLK_S0D3_HSC 19
#define R8A779F0_CLK_S0D4_HSC 20
#define R8A779F0_CLK_S0D6_HSC 21
#define R8A779F0_CLK_S0D12_HSC 22
#define R8A779F0_CLK_S0D2_CC 23
#define R8A779F0_CLK_CL 24
#define R8A779F0_CLK_CL16M 25
#define R8A779F0_CLK_CL16M_MM 26
#define R8A779F0_CLK_CL16M_RT 27
#define R8A779F0_CLK_CL16M_PER 28
#define R8A779F0_CLK_CL16M_HSC 29
#define R8A779F0_CLK_Z0 30
#define R8A779F0_CLK_Z1 31
#define R8A779F0_CLK_ZB3 32
#define R8A779F0_CLK_ZB3D2 33
#define R8A779F0_CLK_ZB3D4 34
#define R8A779F0_CLK_SD0H 35
#define R8A779F0_CLK_SD0 36
#define R8A779F0_CLK_RPC 37
#define R8A779F0_CLK_RPCD2 38
#define R8A779F0_CLK_MSO 39
#define R8A779F0_CLK_SASYNCRT 40
#define R8A779F0_CLK_SASYNCPERD1 41
#define R8A779F0_CLK_SASYNCPERD2 42
#define R8A779F0_CLK_SASYNCPERD4 43
#define R8A779F0_CLK_DBGSOC_HSC 44
#define R8A779F0_CLK_RSW2 45
#define R8A779F0_CLK_OSC 46
#define R8A779F0_CLK_ZR 47
#define R8A779F0_CLK_CPEX 48
#define R8A779F0_CLK_CBFUSA 49
#define R8A779F0_CLK_R 50
#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
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